The present invention generally relates to semiconductor packages and more particularly to semiconductor packages and methods of making Dual Flat Non-Leaded (DFN) semiconductor packages.
Quad Flat Non-Leaded (QFN) semiconductor packages are well known in the art. QFN semiconductor packages are widely used in high pin out IC package applications. For example, a QFN semiconductor package is disclosed in U.S. patent application Publication 2002/0177254 entitled “Semiconductor Package and Method for Making the Same”. The disclosed semiconductor package includes a plurality of connection pads and an embedded die. The connection pads at least partially enclose a die receiving area. An insulator is disposed in the die receiving area and the die is attached to the insulator. The die has a plurality of die bond pads. A plurality of connectors connect the die bond pads to respective connection pads. An encapsulant at least partially encapsulates the connection pads, insulator and die. The connection pads and insulator have exposed surfaces on an outer surface of the encapsulant. The exposed surfaces are substantially co-planar with the outer surface of the encapsulant. A resulting semiconductor package is shown in FIG. 1A and FIG. 1B.
It has been proposed to use DFN semiconductor packages in power MOSFET applications. In power MOSFET applications a major concern relates to thermal and electrical performance as well as to thermally induced stresses to the semiconductor package. QFN packages of the prior art do not provide the requisite thermal properties for such applications.
There is therefore a need in the art for a DFN semiconductor package having good thermal and electrical performance properties. Preferably such a DFN semiconductor package provides for an effective thermal dissipation path. Preferably such a DFN semiconductor package provides for reduced electrical resistance and inductance.